Dynamic Yield Analysis and Enhancement of FPGA Reconfigurable Memory Systems

This paper addresses the issues of field programmable gate arrays (FPGA) reconfigurable memory systems with faulty physical memory cells and proposes yield measurement techniques. Static yield (i.e., the yield which does not take into account the inherited redundancy utilization for repair) and dynamic yield (i.e., the yield which takes into account the inherited redundancy utilization for repair) of FPGA reconfigurable memory systems and their characteristics are extensively analyzed. Yield enhancement of conventional memory systems relies on additional redundancy, but FPGA reconfigurable memory systems have inherited redundancy and customizability. Thus, they can accommodate numerous target memory configurations, and redundant memory cells, if any, can be used as spares to enhance the dynamic yield of a target memory configuration. Three fundamental strategies are introduced and analyzed; i.e., redundant bit utilization, redundant word utilization, and a combination of both. Mathematical analysis of those techniques also has been conducted to study their effects on the yield. Selecting the most yield enhancing logical memory configuration which can accommodate a target memory requirement among the candidate configurations is referred to as optimal fitting. Optimal fitting algorithms for single configuration fitting, sequential reconfiguration system fitting, and concurrent reconfiguration system fitting are investigated based on the proposed yield analysis techniques

Post-Configuration Testing of Asynchronous Nanowire Crossbar Architecture

An asynchronous nanowire crossbar architecture has been recently proposed to eliminate the clock distribution network from conventional clocked counterpart. The proposed clock-free architecture is envisioned to enhance the manufacturability with simpler periodic structure and to improve the robustness by removing various timing-related failure modes. Even though the proposed clock-free architecture has numerous merits over its clocked counterpart, it is still not free from high defect rates induced by nondeterministic nanoscale assembly. In order to address this issue, our research team has been working on developing test schemes for effective mapping of threshold gates onto programmable gate macro blocks (PGMB). We have come up with a novel functional test approach which uses prioritized input tuples to effectively stimulate coinciding defects in configured PGMB. Numerous preliminary plots and results obtained till date prove that this scheme can be used to achieve high test efficiency for any threshold gate. The main motivation behind this research is to propose a comprehensive test scheme which can achieve high enough test coverage with acceptable test overhead. Parametric simulation results using MATLAB have been used to show potential performance of this testing scheme

Locally Synchronous, Globally Asynchronous Design for Quantum-Dot Cellular Automata (LSGA QCA)

The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synchronize data flows, and the way to power QCA cells, make the design of QCA circuits quite different from VLSI and introduce a variety of new design challenges and the most severe challenges are due to the fact that the overall timing of a QCA circuit is mainly dependent upon its layout. This fact is commonly referred to as the layout-timing problem. To circumvent the problem, a novel self-timed circuit design technique referred to as the Locally Synchronous, Globally Asynchronous Design for QCA is proposed in this paper. The proposed technique can significantly reduce the layout-timing dependency from the global network of QCA devices in a circuit; therefore, considerably flexible QCA circuit design will be possible

Locally Synchronous, Globally Asynchronous Design for Quantum-Dot Cellular Automata (LSGA QCA)

The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synchronize data flows, and the way to power QCA cells, make the design of QCA circuits quite different from VLSI and introduce a variety of new design challenges and the most severe challenges are due to the fact that the overall timing of a QCA circuit is mainly dependent upon its layout. This fact is commonly referred to as the layout-timing problem. To circumvent the problem, a novel self-timed circuit design technique referred to as the Locally Synchronous, Globally Asynchronous Design for QCA is proposed in this paper. The proposed technique can significantly reduce the layout-timing dependency from the global network of QCA devices in a circuit; therefore, considerably flexible QCA circuit design will be possible

Dynamic Yield Analysis and Enhancement of FPGA Reconfigurable Memory Systems

This paper addresses the issues of field programmable gate arrays (FPGA) reconfigurable memory systems with faulty physical memory cells and proposes yield measurement techniques. Static yield (i.e., the yield which does not take into account the inherited redundancy utilization for repair) and dynamic yield (i.e., the yield which takes into account the inherited redundancy utilization for repair) of FPGA reconfigurable memory systems and their characteristics are extensively analyzed. Yield enhancement of conventional memory systems relies on additional redundancy, but FPGA reconfigurable memory systems have inherited redundancy and customizability. Thus, they can accommodate numerous target memory configurations, and redundant memory cells, if any, can be used as spares to enhance the dynamic yield of a target memory configuration. Three fundamental strategies are introduced and analyzed; i.e., redundant bit utilization, redundant word utilization, and a combination of both. Mathematical analysis of those techniques also has been conducted to study their effects on the yield. Selecting the most yield enhancing logical memory configuration which can accommodate a target memory requirement among the candidate configurations is referred to as optimal fitting. Optimal fitting algorithms for single configuration fitting, sequential reconfiguration system fitting, and concurrent reconfiguration system fitting are investigated based on the proposed yield analysis techniques

Teaching Nanotechnology by Introducing Crossbar-Based Architecture and Quantum-Dot Cellular Automata

The end of photolithography as the driver for Moore\u27s law is predicted within seven to twelve years and six different emerging technologies (mostly nanoscale) are expected to replace the current CMOS-based system integration paradigm. As nanotechnology is emerging, (1) there is a strong need for well-educated nanoscale systems engineers by industry, and (2) research and education efforts are also called to overcome numerous nanoscale systems issues. This paper is to propose a way to teach nanotechnology by introducing two emerging technologies: crossbar-based nanoarchitecture and quantum-dot cellular automata

Evaluating Performance Tradeoff in Defect-Tolerant Gate Programming Techniques for the Clock-Free Nanowire Crossbar Architecture

A novel asynchronous nanowire crossbar architecture has been recently proposed by authors\u27 research group. The proposed clock-free architecture provides numerous significant benefits over its clocked counterparts which include better manufacturability, scalability, modularity and robustness. We also proposed various gate mapping and reconfiguration algorithms for defect-tolerant programming of PGMB (programmable gate macro blocks) - which is the primary building block of the proposed architecture. These algorithms were tested by simulations and a variety of parameter values were applied to show their performance characteristics. The most important performance metric of the proposed techniques is the programmability (i.e., the ratio of successfully programmed gates to the total number of gates). However, algorithms with higher programmability should come with higher time/space requirements. In this work, we will evaluate the tradeoff between programmability and time/space requirements and suggest a way to find the most suitable algorithm with acceptable combination of programmability and time/space requirements

Protection of Artists\u27 Rights under the Korean Copyright Law

The term artists includes film, television ( TV ), stage, and musical actors and actresses ( actors ), pop singers and musicians, dancers, fashion models, and classical musicians. Although the same analysis can be applied to all of the categories above mentioned, this article solely focuses on pop singers and actors. The Copyright Act of Korea ( Copyright Act ) defines Siryun ( public performance ) as the entertainment activities of artists, and uses Siryunja ( performer ) instead of entertainer as a legal term for artists

Defect Characterization and Yield Analysis of Array-Based Nanoarchitecture

With molecular-scale materials and fabrication techniques recently developed, high-density computing systems in nanometer domain emerge. An array-based nanoarchitecture has been recently proposed based on nanowires such as carbon nanotubes (CNTs), silicon nanowires (SiNWs). High-density nanoarray-based systems consisting of nanometer-scale elements are likely to have many imperfections; thus, defect-tolerance is considered as one of the most significant challenges. In this paper, we propose a probabilistic yield model for the array-based nanoarchitecture. The proposed yield model can be used 1) to accurately estimate the raw and net array densities, and 2) to design and optimize more defect and fault-tolerant systems based on the array-based nanoarchitecture

Redundancy Optimization for Clock-Free Nanowire Crossbar Architecture

In this paper a method is being proposed to find the optimal dimension of Programmable Gate Macro Block (PGMB) in clock-free nanowire crossbar architecture. A PGMB is a nanowire crossbar matrix with discrete number of rows and columns on which the NCL (Null Convention Logic) gates can be programmed. This method uses inherent redundancy to route through defective crosspoints. A 6 X 10 defect-free crossbar can be used to program any of the 27 threshold gates. Due to imperfections and variations in nanoscale manufacturing process, high defect densities are anticipated. Thus, such defects should be located when tested and the logic has to be rerouted around them to maintain proper functionality. This paper discusses this problem and tried to find an optimal solution through simulations. In the final submission, more effective logic mapping techniques will be proposed and validated